This disclosure relates in general to the field of electronic devices. More specifically, this disclosure relates to a system and method for testing component IC chips.
Integrated circuit (IC) chips are a collection of small electronic devices integrated together to perform a number of different functions. As manufacturing techniques have developed, the size of these electronic devices has decreased while the density of electronic devices and the functionality of the IC chips has increased. IC chips are utilized in numerous applications in computer systems and other devices. Often, computer systems incorporate multiple IC chips each IC chip performing a specific function within the system. The IC chips, when installed on a common circuit board, are often referred to as xe2x80x9con-boardxe2x80x9d chips.
As the complexity of IC chips increases, the testing of IC chips takes on increased significance. One type of testing which is frequently used is JTAG testing, a standardized testing protocol. This standard has been adopted by the Institute of Electrical and Electronics Engineers, Inc. as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture, and is incorporated herein be reference. Simply, JTAG testing involves sending an IC chip a selected test input and receiving test output from the IC chip. The test output is then compared with the expected output to evaluate the functionality of the IC chip.
Often, chips are individually tested for functionality when they are manufactured using specialized testing equipment. IC chips may be tested prior to being used to determine whether they will function according to their design. This testing often provides an effective means of quality control.
However, some defects and malfunctions may arise after this initial testing. These defects may seriously effect IC chip performance and functionality causing the IC chip to lose efficiency, malfunction, or cease functioning. In computer systems with multiple component IC chips, the defect or malfunction of one component IC chip may effect the other components of the system causing the entire system to lose efficiency, malfunction, or stop functioning altogether.
JTAG testing equipment may be used to test IC chips within a system to diagnose a problem or as part of a maintenance regimen. Such testing often requires skilled technicians to travel to a system site, connect the JTAG test equipment, and operate the JTAG test equipment. Often the system must be shut down, taken off line, or disassembled to perform these tests. JTAG testing using JTAG equipment consumes valuable time and resources. Traveling time and time spent connecting the JTAG equipment uses valuable technician time. Also, before testing is complete, a system may malfunction or be removed from service until a skilled technician is available to connect and operate the JTAG testing equipment. This time may seriously detract from system functionality, efficiency, and profitability.
Therefore, a need has arisen for a system and method for testing component IC chips using JTAG test standards which does not require the use of separate testing equipment.
A further need has arisen for a system and method for performing JTAG tests on component IC chips without interrupting system operation.
In accordance with teachings of the present disclosure, a system and method are described for testing component IC chips. In one aspect, the system includes a management controller that has an embedded JTAG test routine operable to test one or more component IC chips associated with the management controller. The system also includes a memory associated with the management controller and the management controller is further operable to save a JTAG test routine result within the memory. More specifically, the management controller is preferably operable to test one or more associated component IC chips using the embedded JTAG test routine during boot up of the system.
In another aspect, the system includes a server that has a management controller and at least one component IC chip. The management controller is associated with the at least one component IC chip. A memory is also associated with the server. The management controller preferably has an embedded JTAG test routine which is operable to test the at least component IC chip and the management controller is further operable to save a JTAG test routine result for the at least one component IC chip in the memory.
More specifically, the embedded JTAG test routine may be incorporated into an embedded server boot initialization system test (ESBIST) within the management controller.
In yet another aspect, a method is disclosed for testing component IC chips in a computer system that includes installing a JTAG test routine in a management controller associated with the computer system. At least one component IC chip is tested using the JTAG test routine. Test results from the JTAG test routine may then be saved in a test log.
The present disclosure has many important technical advantages. One technical advantage is installing a JTAG test routine in the management controller. This allows the system to perform JTAG testing of system component IC chips without separate JTAG testing equipment. This also eliminates the need for a skilled technician to visit a system site and disassemble a system to perform JTAG tests. Another technical advantage is performing JTAG testing on component IC chips during normal boot up of the system. This allows testing to be performed without interrupting system operations.